-- EG7014 Controller 'Sessoku'-ism version
-- part1(CPU,VRAM interface and Timing generate)
-- (c)2003 A.Hiramatsu
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library aim;
use aim.components.all;
library pls;
use pls.attributes.all;
entity lcd_mor0 is
Port ( clk : in std_logic;
ca : in std_logic_vector(18 downto 0);
cd : inout std_logic_vector(7 downto 0);
crd : in std_logic;
cwr : in std_logic;
ccs : in std_logic;
cwait : out std_logic;
ma : out std_logic_vector(18 downto 0);
md : inout std_logic_vector(7 downto 0);
mrd : out std_logic;
mwr : out std_logic;
cp1 : out std_logic;
cp2 : out std_logic;
do : out std_logic_vector(3 downto 0);
frm : out std_logic);
end lcd_mor0;
architecture behavioral of lcd_mor0 is
signal div:std_logic_vector(4 downto 0);
signal icp1,icp2:std_logic;
signal x:std_logic_vector(6 downto 0);
signal y:std_logic_vector(7 downto 0);
signal q:std_logic_vector(7 downto 0);
signal iwait:std_logic;
signal ibsel:std_logic;
signal ima:std_logic_vector(18 downto 0);
signal ifrm:std_logic;
signal iadr:std_logic_vector(14 downto 0);
attribute PWR_MODE of cp1 : signal is "low";
attribute PWR_MODE of cp2 : signal is "low";
attribute PWR_MODE of do : signal is "low";
attribute PWR_MODE of frm :signal is "low";
attribute PWR_MODE of div : signal is "low";
attribute PWR_MODE of icp1 : signal is "low";
attribute PWR_MODE of icp2 : signal is "low";
attribute PWR_MODE of x : signal is "low";
attribute PWR_MODE of y : signal is "low";
attribute PWR_MODE of q : signal is "low";
attribute PWR_MODE of ifrm : signal is "low";
begin
process(clk)
begin
if(clk'event and clk='1') then
if(div="10111") then
div<="00000";
if(x="1010000") then
if(y="11000111") then
y<="00000000";
else
y<=y+1;
end if;
x<="0000000";
else
x<=x+1;
end if;
else
div<=div+1;
end if;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1') then
if((div="00101")or(div="10001")) then
icp2<='1';
elsif((div="01011")or(div="10111")) then
icp2<='0';
end if;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1') then
if(div="00101") then
q(7 downto 0 )<=md(7 downto 0);
elsif(div="10001") then
q(7 downto 4)<=q(3 downto 0);
end if;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1') then
if(x="0000000") then
if(div="00100") then
icp1<='1';
elsif(div="10010") then
icp1<='0';
end if;
end if;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1') then
if(div="00000") then
if((x="0000000")and(y="00000001")) then
ifrm<='1';
else
ifrm<='0';
end if;
end if;
end if;
end process;
cp1 <= icp1;
cp2 <= icp2;
frm <= ifrm;
do(3 downto 0) <= q(7 downto 4);
iadr <= y & x;
process(clk)
begin
if(clk'event and clk='1') then
if(div="00000") then
iwait<='1';
elsif(div="00110") then
iwait<='0';
end if;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1') then
if(div="00011") then
ibsel<='1';
elsif(div="00101") then
ibsel<='0';
end if;
end if;
end process;
process(crd,ccs,md)
begin
if(crd='1' or ccs='1') then cd <= "ZZZZZZZZ";
else cd <= md;
end if;
end process;
process(crd,ccs,ibsel,cd)
begin
if((crd='0' and ccs='0') or ibsel='1') then md <= "ZZZZZZZZ";
else md <= cd;
end if;
end process;
process(ibsel,iadr,ca)
begin
if(ibsel='1') then
ima <= "0100" & iadr;
else
ima(18) <= ca(18);
ima(17) <= not ca(17);
ima(16 downto 0) <= ca(16 downto 0);
end if;
end process;
cwait <= not( not ccs and iwait);
ma <= ima;
mrd <= not(ibsel or (not crd and not ccs));
mwr <= not(not ibsel and not cwr and not ccs);
end behavioral;
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