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-- G2436 Controller 2-plane version
-- (c)2003 A.Hiramatsu
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd4_2 is
Port ( clk : in std_logic;
ca : in std_logic_vector(18 downto 0);
cd : inout std_logic_vector(7 downto 0);
crd : in std_logic;
cwr : in std_logic;
ccs : in std_logic;
cwait : out std_logic;
ma : out std_logic_vector(18 downto 0);
md : inout std_logic_vector(7 downto 0);
mrd : out std_logic;
mwr : out std_logic;
cp1 : out std_logic;
cp2 : out std_logic;
do : out std_logic_vector(3 downto 0);
frm : out std_logic;
m : out std_logic);
end lcd4_2;
architecture behavioral of lcd4_2 is
signal div:std_logic_vector(5 downto 0);
signal icp1,icp2:std_logic;
signal b:std_logic;
signal x:std_logic_vector(4 downto 0);
signal y:std_logic_vector(5 downto 0);
signal q:std_logic_vector(7 downto 0);
signal q2:std_logic_vector(7 downto 0);
signal iwait:std_logic;
signal ibsel:std_logic;
signal ipsel:std_logic;
signal ima:std_logic_vector(18 downto 0);
signal ifrm:std_logic;
signal im:std_logic;
signal iadr:std_logic_vector(10 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1') then
if(div="101011") then
if(icp2='0') then
icp1 <= '0';
if(b='1') then
q <= md or q2;
if(x="11101") then
y <= y+1;
x <= "00000";
else
x <= x+1;
end if;
end if;
b <= not b;
else
if(b='1' and x="00000") then
icp1 <= '1';
end if;
end if;
icp2 <= not icp2;
div <= "000000";
else
if(b='1' and div="101001") then
q2 <= md;
end if;
div <= div+1;
end if;
end if;
end process;
cp1 <= icp1;
cp2 <= icp2;
do(3) <= (q(7) and not b) or (q(3) and b);
do(2) <= (q(6) and not b) or (q(2) and b);
do(1) <= (q(5) and not b) or (q(1) and b);
do(0) <= (q(4) and not b) or (q(0) and b);
iadr <= y & x;
process(clk)
begin
if(clk'event and clk='1') then
if(b='1' and icp2='0') then
if(div="100111") then
ibsel <= '1';
ipsel <= '0';
elsif(div="101001") then
ipsel <= '1';
elsif(div="101011") then
ibsel <= '0';
end if;
if(div="100100") then
iwait <= '1';
end if;
elsif(b='0' and icp2='1' and div="000000") then
iwait <= '0';
end if;
end if;
end process;
process(crd,ccs,md)
begin
if(crd='1' or ccs='1') then cd <= "ZZZZZZZZ";
else cd <= md;
end if;
end process;
process(crd,ccs,ibsel,cd)
begin
if((crd='0' and ccs='0') or ibsel='1') then md <= "ZZZZZZZZ";
else md <= cd;
end if;
end process;
process(ibsel,iadr,ca,ipsel)
begin
if(ibsel='1') then
ima <= "0100000" & ipsel & iadr;
else
ima(18) <= ca(18);
ima(17) <= not ca(17);
ima(16 downto 0) <= ca(16 downto 0);
end if;
end process;
cwait <= not( not ccs and iwait);
ma <= ima;
mrd <= not(ibsel or (not crd and not ccs));
mwr <= not(not ibsel and not cwr and not ccs);
process(clk)
begin
if(clk'event and clk='1') then
if(iadr="00000000001" and b='0' and div="101011") then
ifrm <= '1';
else
if(iadr="00000100001" and b='0' and div="101011") then
ifrm <= '0';
end if;
end if;
end if;
end process;
process(ifrm)
begin
if(ifrm'event and ifrm='0') then
im <= not im;
end if;
end process;
frm <= ifrm;
m <= im;
end behavioral;
-- G2436 Controller character display version
-- (c)2003 A.Hiramatsu
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd4_c is
Port ( clk : in std_logic;
ca : in std_logic_vector(18 downto 0);
cd : inout std_logic_vector(7 downto 0);
crd : in std_logic;
cwr : in std_logic;
ccs : in std_logic;
cwait : out std_logic;
ma : out std_logic_vector(18 downto 0);
md : inout std_logic_vector(7 downto 0);
mrd : out std_logic;
mwr : out std_logic;
cp1 : out std_logic;
cp2 : out std_logic;
do : out std_logic_vector(3 downto 0);
frm : out std_logic;
m : out std_logic);
end lcd4_c;
architecture behavioral of lcd4_c is
signal div:std_logic_vector(5 downto 0);
signal icp1,icp2:std_logic;
signal b:std_logic;
signal x:std_logic_vector(4 downto 0);
signal y:std_logic_vector(5 downto 0);
signal q:std_logic_vector(7 downto 0);
signal chr:std_logic_vector(7 downto 0);
signal iwait:std_logic;
signal ibsel:std_logic;
signal icgsel:std_logic;
signal ima:std_logic_vector(18 downto 0);
signal ifrm:std_logic;
signal im:std_logic;
signal iadr:std_logic_vector(10 downto 0);
signal chadr:std_logic_vector(10 downto 0);
signal cgadr:std_logic_vector(10 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1') then
if(div="101011") then
if(icp2='0') then
icp1 <= '0';
if(b='1') then
q <= md;
if(x="11101") then
y <= y+1;
x <= "00000";
else
x <= x+1;
end if;
end if;
b <= not b;
else
if(b='1' and x="00000") then
icp1 <= '1';
end if;
end if;
icp2 <= not icp2;
div <= "000000";
else
if(b='1' and div="101001") then
chr <= md;
end if;
div <= div+1;
end if;
end if;
end process;
cp1 <= icp1;
cp2 <= icp2;
do(3) <= (q(7) and not b) or (q(3) and b);
do(2) <= (q(6) and not b) or (q(2) and b);
do(1) <= (q(5) and not b) or (q(1) and b);
do(0) <= (q(4) and not b) or (q(0) and b);
iadr <= y & x;
chadr <= "000" & y(5 downto 3) & x;
cgadr <= chr & y(2 downto 0);
process(clk)
begin
if(clk'event and clk='1') then
if(b='1' and icp2='0') then
if(div="100111") then
ibsel <= '1';
icgsel <= '0';
elsif(div="101001") then
icgsel <= '1';
elsif(div="101011") then
ibsel <= '0';
end if;
if(div="100100") then
iwait <= '1';
end if;
elsif(b='0' and icp2='1' and div="000000") then
iwait <= '0';
end if;
end if;
end process;
process(crd,ccs,md)
begin
if(crd='1' or ccs='1') then cd <= "ZZZZZZZZ";
else cd <= md;
end if;
end process;
process(crd,ccs,ibsel,cd)
begin
if((crd='0' and ccs='0') or ibsel='1') then md <= "ZZZZZZZZ";
else md <= cd;
end if;
end process;
process(ibsel,iadr,ca,icgsel,chadr,cgadr)
begin
if(ibsel='1') then
if(icgsel='0') then
ima <= "01000001" & chadr;
else
ima <= "01000000" & cgadr;
end if;
else
ima(18) <= ca(18);
ima(17) <= not ca(17);
ima(16 downto 0) <= ca(16 downto 0);
end if;
end process;
cwait <= not( not ccs and iwait);
ma <= ima;
mrd <= not(ibsel or (not crd and not ccs));
mwr <= not(not ibsel and not cwr and not ccs);
process(clk)
begin
if(clk'event and clk='1') then
if(iadr="00000000001" and b='0' and div="101011") then
ifrm <= '1';
else
if(iadr="00000100001" and b='0' and div="101011") then
ifrm <= '0';
end if;
end if;
end if;
end process;
process(ifrm)
begin
if(ifrm'event and ifrm='0') then
im <= not im;
end if;
end process;
frm <= ifrm;
m <= im;
end behavioral;
-- G2436 Controller character & graphic display version
-- (c)2003 A.Hiramatsu
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd4_cg is
Port ( clk : in std_logic;
ca : in std_logic_vector(18 downto 0);
cd : inout std_logic_vector(7 downto 0);
crd : in std_logic;
cwr : in std_logic;
ccs : in std_logic;
cwait : out std_logic;
ma : out std_logic_vector(18 downto 0);
md : inout std_logic_vector(7 downto 0);
mrd : out std_logic;
mwr : out std_logic;
cp1 : out std_logic;
cp2 : out std_logic;
do : out std_logic_vector(3 downto 0);
frm : out std_logic;
m : out std_logic);
end lcd4_cg;
architecture behavioral of lcd4_cg is
signal div:std_logic_vector(5 downto 0);
signal icp1,icp2:std_logic;
signal b:std_logic;
signal x:std_logic_vector(4 downto 0);
signal y:std_logic_vector(5 downto 0);
signal q:std_logic_vector(7 downto 0);
signal q2:std_logic_vector(7 downto 0);
signal chr:std_logic_vector(7 downto 0);
signal iwait:std_logic;
signal ibsel:std_logic;
signal icsel:std_logic;
signal icgsel:std_logic;
signal ima:std_logic_vector(18 downto 0);
signal ifrm:std_logic;
signal im:std_logic;
signal iadr:std_logic_vector(10 downto 0);
signal chadr:std_logic_vector(10 downto 0);
signal cgadr:std_logic_vector(10 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1') then
if(div="101011") then
if(icp2='0') then
icp1 <= '0';
if(b='1') then
q <= md or q2;
if(x="11101") then
y <= y+1;
x <= "00000";
else
x <= x+1;
end if;
else
q(7 downto 4) <= q(3 downto 0);
end if;
b <= not b;
else
if(b='1' and x="00000") then
icp1 <= '1';
end if;
end if;
icp2 <= not icp2;
div <= "000000";
else
if(div="100111") then
q2 <= md;
elsif(div="101001") then
chr <= md;
end if;
div <= div+1;
end if;
end if;
end process;
cp1 <= icp1;
cp2 <= icp2;
do(3) <= (q(7) and not b) or (q(3) and b);
do(2) <= (q(6) and not b) or (q(2) and b);
do(1) <= (q(5) and not b) or (q(1) and b);
do(0) <= (q(4) and not b) or (q(0) and b);
iadr <= y & x;
chadr <= "000" & y(5 downto 3) & x;
cgadr <= chr & y(2 downto 0);
process(clk)
begin
if(clk'event and clk='1') then
if(b='1' and icp2='0') then
if(div="100101") then
ibsel <= '1';
icsel <= '0';
icgsel <= '0';
elsif(div="100111") then
icsel <= '1';
elsif(div="101001") then
icgsel <= '1';
elsif(div="101011") then
ibsel <= '0';
end if;
if(div="100010") then
iwait <= '1';
end if;
elsif(b='0' and icp2='1' and div="000000") then
iwait <= '0';
end if;
end if;
end process;
process(crd,ccs,md)
begin
if(crd='1' or ccs='1') then cd <= "ZZZZZZZZ";
else cd <= md;
end if;
end process;
process(crd,ccs,ibsel,cd)
begin
if((crd='0' and ccs='0') or ibsel='1') then md <= "ZZZZZZZZ";
else md <= cd;
end if;
end process;
process(ibsel,iadr,ca,icsel,icgsel,chadr,cgadr)
begin
if(ibsel='1') then
if(icsel='0') then
ima <= "01000000" & iadr;
else
if(icgsel='0') then
ima <= "01000010" & chadr;
else
ima <= "01000001" & cgadr;
end if;
end if;
else
ima(18) <= ca(18);
ima(17) <= not ca(17);
ima(16 downto 0) <= ca(16 downto 0);
end if;
end process;
cwait <= not( not ccs and iwait);
ma <= ima;
mrd <= not(ibsel or (not crd and not ccs));
mwr <= not(not ibsel and not cwr and not ccs);
process(clk)
begin
if(clk'event and clk='1') then
if(iadr="00000000001" and b='0' and div="101011") then
ifrm <= '1';
else
if(iadr="00000100001" and b='0' and div="101011") then
ifrm <= '0';
end if;
end if;
end if;
end process;
process(ifrm)
begin
if(ifrm'event and ifrm='0') then
im <= not im;
end if;
end process;
frm <= ifrm;
m <= im;
end behavioral;